Many dynamic Random Access Memory (RAM) systems use a multiplexed address bus. This arrangement, for example, requires that half of the necessary address bits be consecutively placed on the address bus (e.g., first the row address bits and then the column address bits). No accurate memory access can, of course, occur until the entire address has been strobed into the memory. Reducing the time required to strobe in the row address bits, switch the bits on the address bus from row address bits to column address bits, and then strobe these column address bits into the memory is, therefore, critical to enhancing the speed of memory operations.
Previous memory systems rely on fixed delays to properly control memory accesses via a multiplexed address bus. A first fixed delay line has been used to ensure that sufficient time has elapsed between generation of the row address strobe (RAS) bits and the switching of the address bus from row address bits to column address bits. During this first fixed delay period the row address bits present on the address bus are strobed into the memory by the RAS bits. If the first fixed delay is set too short, the row address bits will not be strobed into the memory before the row address bits are replaced by column address bits. This would result in the erroneous addressing and subsequent accessing of an unwanted memory location. If this first fixed delay is set too long the memory access times will be unnecessarily long and memory and associated system operations will, therefore, be slower.
The second fixed delay line employed in current memory systems is inserted between switching the address bus from row to column address bits and the generation of column address strobe (CAS) bits which strobe these column address bits into memory. This second fixed delay ensures that a sufficient amount of time elapses between these two events so that all the bits on the address bus will indeed be column address bits and not prior row address bits which have yet to be switched or are in the process of being switched to column address bits. As with the first fixed delay period described above, the wrong memory location will be addressed and then accessed if the second fixed delay is set too short and memory operations will be unduly long if this second fixed delay is set too long.
The two fixed delays used in previous memory systems are also not located on the same integrated circuit as the RAS generator, CAS generator and the address bus multiplexor (e.g., due to temperature induced circuit timing delays, power supply variations or technology variations). This can result in a lack of tracking between the fixed delay lines and the RAS and CAS generators and the address bus multiplexor. This lack of tracking may require setting the two fixed delay periods longer than actually necessary in order to ensure that these delays will not be seen as too short due to tracking differences. The result is an accurate, but slowly operating memory system.